Artificial intelligence (AI) is changing the way the world builds and uses computer chips. From massive data centers to devices at the edge of the network, AI requires that chips continue to grow faster, smaller, and more power efficient.
For decades, Moore’s Law, which accurately predicted that the number of transistors on a computer chip would double roughly every two years, has helped keep the industry moving forward.
Unfortunately, traditional measurement methods through complementary metal oxide semiconductor (CMOS) devices, or FinFETs, which extend Moore’s Law, have reached their limits. The industry now faces a critical challenge: trying to keep chip technology moving when the old rule of thumb no longer applies.
The industry’s answer is Gateway All-In-One (GAA). This design completely encapsulates the gate material on all sides, including the control portion of the chip, known as the gate, which carries the electrical current.
This gives engineers more precise control over how electricity flows through the chip, enabling GAA devices to perform better even as the industry continues on to the next node. This also allows for more power without taking up more space.
New bottlenecks
But the GAA is not perfect. While it solves challenges through lower energy consumption and more efficient use of space, it shifts the bottleneck to other areas.
Specifically, older chips encounter resistance — anything that slows down electricity — from within the channel. Most of the resistance comes from the contact points and areas where current enters and exits.
To fix this problem, engineers added substances called dopants to help electricity flow better. But during this activation process, similar materials can inadvertently spread to nearby places on the chip that must be degrafted.
When this happens, it can not only affect performance but create additional issues in the chip such as increased leakage, changing threshold voltage or introducing contrast.
Another challenge stems from the manufacturing process, specifically when layers of silicon and germanium (SiGe) are removed to form parts of the chip.
This can leave rough surfaces and interfere with how smoothly electricity flows through appliances. Later, when metal contact points are added on top, this creates more resistance at the point where the metal and silicone meet.
In sum, GAA may address the challenges of static electricity, but it also introduces new challenges. This is where advanced materials come into play.
Atomic scale materials, major repairs
To meet these new challenges, chipmakers are turning to advanced materials and working at the atomic level to help realize the full potential of GAA.
Here’s how these new materials help:
- Preventing the spread of unwanted steroids: Inserting an advanced barrier between the heavily doped and non-doped areas can prevent leakage of doping to other areas of the chip. This containment is essential to enhance performance.
- Surface smoothing: Rough surfaces at the atomic level can scatter and slow down electrons. Advanced material engineering can smooth out surfaces that may become uneven while removing sacrificial SiGe layers, reducing this dispersion. This can enhance conveyor movement under normal operating conditions, resulting in faster shifting and better performance, all without requiring more power.
- Enhance strength without compromising size: Advanced materials allow engineers to incorporate thinner performance structures into the same space. This change can boost the current per fingerprint by about 10% without increasing the chip size.
- Reduce contact resistance: As device dimensions get smaller, the electrical contact resistance at the point where the metal contacts the silicon becomes a major limiting factor. By modifying materials at these junctions, engineers can significantly reduce resistance and unlock greater efficiency.
Looking forward
The explosive growth of artificial intelligence is driving a fundamental shift in how the industry thinks about computing efficiency. Engineers now face an increasingly complex trade-off between power, performance, space and cost (PPAC).
In the past, the industry has relied on incremental improvements to stay on track, but with the scale and intensity of AI pushing existing architectures to their limits, these small gains are no longer enough.
To unleash the next wave of progress, the industry needs a more transformative transformation, one that resets the foundation and enables further improvements to continue making impact.
The next node, also referred to as the Angstrom Era, will accelerate innovations in advanced materials beyond what is possible today to advance across the PPAC equation. GAA is just the beginning.
To continue shrinking and improving chips for massive AI systems, engineers are exploring new ways to do more with less. These advances in advanced materials are enabling industry to achieve more performance with less space and power, leading to smarter, more sustainable computing across the board.
Beyond GAA, the industry is already working on a new structure called CFET, or complementary FET, which may take us a few more generations before we start looking at 3D structures such as stacked CFETs to keep Moore’s Law moving forward.
One thing is certain, new advanced materials will be needed every step of the way to unleash the performance that these new transistor structures are designed to enable.
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